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XenoTech Software brings to the North American market a broad range of leading edge verification products that address the complexities of protocols, technologies and flows within their target application areas.
These verification products have been proven to:
- Increase the productivity of design and verification teams
- Reduce the cost of design verification
- Create a methodology of reuse across design hierarchies and distributed design teams
- Increase design quality prior to tape-out
For more information, or to arrange an evaluation, please contact us
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Analog Mixed-Signal Verification Solutions |
AMS
Verification Kit
Creates
an automated, coverage driven verification environment and methodology for top
and block-level mixed-signal designs. An extensible set of configurable
pre-verified verification components that unify Specman Elite and a mixed-signal
simulator to create an automated AMS verification environment.
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Design for Test Verification Solutions |
STIL Verifier
STIL Verifier is a flexible EDA solution that automates the flow to and from the design verification environment (simulation) and silicon test (ATE).
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IEEE
1500 Verification IP
The IEEE 1500 (or SECT) VIP verifies a chain of one or more IEEE1500 compliant core wrappers. It identifies wrapper design bugs, brings out protocol compatibility issues to ensure interoperability of testability features.
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IEEE
1149.1 (JTAG)
Verification IP
The IEEE
JTAG eVC is a complete verification environment built around the IEEE
1149.1-2001 (JTAG) standard. Combine this eVC with the new IEEE 1500 eVC for a
complete system-on-chip testability infrastructure verification solution.
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Design for Test Verification Kit
Creates a complete and automated DFT verification environment in minutes. Create comprehensive verification plans and audit DFT architectures for post-silicon testability. Metric driven increase of quality of manufacturing functionality.
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Processor and Interconnect Verification Solutions |
LPC eVC & UVC
Supporting both SystemVerilog and Specman e, the LPC VIP is used to verify a single LPC interfaced device or a system with multiple LPC-compatible devices.
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OCP
2.1 eVC & UVC
The OCP 2.1 VIP is the most widely deployed OCP verification solution on the market. Fully OCP Functional Verification Guidelines compliant and OCP 2.1 compliant including all
advanced features such as multi-threading and bursts. The UVC enables
multi-language support - 'e' and SystemVerilog.
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PCI version 2.2 eVC and UVC
Supporting both SystemVerilog and Specman e, the PCI VIP is used to verify a single PCI interfaced device or a system with multiple PCI-compatible devices.
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PCI-X eVC and UVC
Supporting both SystemVerilog and Specman e, the PCI-X VIP is used to verify a single PCI-X interfaced device or a system with multiple PCI-X-compatible devices.
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SPI-4 eVC and UVC
Supporting both SystemVerilog and Specman e, the SPI-4 VIP is used to verify a single master/slave SPI-4 core or a system with multiple SPI-4 -compatible devices.
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I2C plus SM Bus 2.0 VIP
Supporting both SystemVerilog and Specman e, the SMBus VIP is used to verify a single SMBus interfaced device or a system with multiple SMBus-compatible devices.
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I2C plus PM Bus 2.0 VIP
Supporting both SystemVerilog and Specman e, the SMBus VIP is used to verify a single PMBus interfaced device or a system with multiple PMBus-compatible devices.
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I2C eVC and UVC
Supporting both SystemVerilog and Specman e, the I2C VIP is used to verify a single I2C interfaced device or a system with multiple I2C connected cores.
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Mass Storage Verification Solutions |
ATAPI eVC and UVC
Supporting the latest versions of the protocol and supporting both SystemVerilog and Specman e languages - these VIPs are the most cost effective way of ensuring design verification coverage of ATAPI core interfaces.
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Compact Flash VIP
A reliable solution for the verification of Compact Flash Host/Slave units.
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CE-ATA
eVC
The Consumer
Electronics Advanced Technology Attachment (CE-ATA) eVC is a complete
verification environment for CE-ATA compliant Host or Device implementations.
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SAS
eVC
The Serial Attached SCSI (SAS) interface eVC is a complete
verification environment for SAS core.
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SATA
eVC and UVC
The SATA eVC and UVC are complete
verification environments for SATA compliant Host or Device implementations.
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Automotive Verification Solutions |
CAN
2.0b eVC
Compliant
with the CAN 2.0B (plus addendum) specification and supports both standard and
extended frames. Generates all frame types such as data, remote, overload and
error frames. Complete built-in set of predefined coverage items and an embedded
protocol-checker.
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LIN
eVC
Compliant
with the latest LIN 2.0 specifications this eVC achieves complete functional
coverage using a complete built in set of predefined coverage items.
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Communications Verification Solutions |
Serial RapidIO
UVC
The SerialRapidIO uVC emulates the behavior of a
SerialRapidIO interfaced core and is used to verify a single device with a SerialRapidIO interface,
or a system containing multiple SerialRapidIO compatible
devices.
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IrDA
eVC
The Infrared
Data Association (IrDA®)
eVC is a powerful verification bundle built around the IrDA Physical Layer
Specification. Ideal for embedded processor applications or system-on-chip
designs.
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UART
16x50
eVC
The
Universal Asynchronous Receiver Transmitter (UART) 16x50 eVC is a complete
device-level verification environment capable of validating industry standard
16550 through 16950 A-D UART designs.
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UART
eVC
The
Universal Asynchronous Receiver Transmitter (UART) eVC is a powerful
verification bundle built around the UART industry standard. This eVC has been
adopted worldwide as a building block for reusable verification platforms.
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