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Verification takes a broader role...
Cadence verification IP claims board language support...
Verification languages: 3 points to ponder beyond "which one?"...
An Analog Mixed-Signal Verification Kit for Verification of Analog-Digital Circuits
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A unified DFT Verification Methodology
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Scenario Builder Increases Value, Verification IP Reuse
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Designing a CE-ATA Verification Environment for SoC Applications
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How are you planning to verify all that DFT?
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Verification News
8/16/07
HDL Design House supports OVM from Cadence and Mentor...
5/22/07
HDL Design House becomes Cadence's Plan-to-Closure Methodology-Qualified Verification Alliance Member...
4/25/07
HDL Design House Releases New SPI-4 uVC to the general market...
4/25/07
HDL Design House Releases New PCI-X uVC to the general market...
4/17/07
HDL Design House Releases New PCI uVC to the general market...
4/12/07
HDL Design House Releases New Low Pin Count (LPC) uVC to the general market...
10/16/06
Globetech Solutions announces STIL Verifier, shortest path between verification and test...
10/6/06
YOGITECH Introduces Industry First OCP Universal Verification Component...
8/7/06
Cadence introduces universal verification components...
6/27/06
TransEDA is in winding down discussions...
6/27/06
Marvell buys Intel's handheld processor unit for $600 million...
6/21/06
Yogitech at CDNLive! EMEA 2006 Nice, France...
6/13/06
Yogitech extends OCP Verification Component Functionality...
6/13/06
OCP-IP Releases Functional Coverage Guidelines...
4/24/06
Scenario Builder Press Release...
4/24/06
Verification: Novices get the IC picture...
2/23/06
Sparks fly at "Bigwig" panel...
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